Built a static-structural FEA of a solder microbump under -55 → 125 °C thermal cycling in ANSYS, quantifying peak stress and per-cycle plastic-strain accumulation, with a 5 → 1 µm mesh study confirming the stress concentration was physical. Authored a physics-based technical review of Integrated Fan-Out (InFO) advanced packaging applying θja and CTE-mismatch strain models. Extracted interconnect R/L/C, simulated transmission-line crosstalk and eye diagrams in ANSYS Electronics, and analyzed chip-level cooling across thermal-interface contact resistance, two-phase immersion boiling, and heat-pipe sizing.
Microsystem Packaging Thermal Simulations
FEA of solder microbumps under thermal cycling, a physics-based review of InFO advanced packaging, and chip-level cooling analysis from immersion boiling to heat pipes.
Role Individual project
Year Purdue, 2025–26
100 MPa peak von Mises stress quantified in a solder microbump under -55 → 125 °C cycling
40+ IEEE Xplore and Google Scholar papers synthesized in the InFO packaging review
- Technologies
- ANSYS
- Capabilities
- Simulation · Technical Communication
- Organizations
- Purdue University
- Research areas
- Microsystems Packaging · Thermal Systems